1. Field of the Invention
The present invention relates to an electronic module, and more particularly, to a multi-package stack module made by stacking a plurality of semiconductor packages.
2. Description of the Related Art
The electronic industry continues to seek products that are lighter, faster, smaller, multi-functional, more reliable and more cost-effective. In order to meet the requirement of the electronic industries, circuit chips must become highly integrated.
However, it is expensive and there are technical limitations to enhancing the density of integration of chips. Therefore, 3-D type semiconductor packaging technologies have been developed and used in order to overcome the above-mentioned problems. In general, a multi-package module made by stacking a plurality of packages in a module is known.
In order to manufacture a multi-package module by using conventional ball grid array type packages, additional electrical connecting means need to be inserted between packages, because the conductive bumps are formed entirely on the rear side of each board and can induce structural mismatch with the chip of the package beneath.
Therefore, the packages in which bump pads are formed in the area peripheral to the chip installation area are usually used for manufacturing multi-package modules as shown in FIG. 1 and FIG. 2.
FIG. 1 is a plan view of a conventional package used in a multi-package module. FIG. 2 is a sectional view of a conventional multi-package module made by stacking a plurality of the conventional packages shown in FIG. 1. The conventional package of FIGS. 1 and 2 comprises a board (140), a chip (112) disposed on the board, a plurality of redistribution patterns (143) formed on the board, a plurality of first bump pads (144) and a plurality of second bump pads (145). The first bump pad (144) is electrically connected to one end of each redistribution pattern (143). The other end of the redistribution patterns (143) is electrically connected to the chip (112). The second bump pads (145) are formed on the rear side of the board (140) and are electrically connected to the first bump pads (144) through via-holes (146). In general, a plurality of bonding pads (114) are formed on the chip (112), and the bonding pads (114) are electrically connected to the redistribution patterns (143) by bonding wires (116). The chip (112) and the bonding wires (116) are usually encapsulated by a resin (160), such as epoxy molding compound (EMC), in order to protect the chip 112 from the adverse effects of the external environment. Solder bumps (170) are usually formed on the second bump pads (145). The solder bumps (170) are used for electrical connection between respective packages.
A plurality of the packages are stacked to form a multi-package stack module (100) as shown in FIG. 2. The stacked packages are electrically connected to each other by the solder bumps (170).
In the conventional multi-package module (100), the chips (112) which are placed in the stacked packages (100) are vertically aligned one with the other. This configuration is employed because the chip installation areas of the stacked packages are all identical. Therefore, each chip (112) is affected not only by the heat it generates, but is also affected by the heat generated by the upper and lower adjacent chips. In addition, the bump pads (144,145) and the solder bumps (170) must be formed in the area peripheral to the chip installation area. Therefore, the area in which the Input/Output terminals can be formed is limited.